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TC58NVG0S3HTA00 2012-08- 31 c 1 toshiba mos digital integrated circuit silicon gate cmos 1g bit (128 m ? 8 bit ) cmos nand e 2 prom description the tc58nvg0s3h ta00 is a single 3.3v 1g bit ( 1, 140 , 850 , 688bits ) nand electrically erasable and programmable read - only memory (nand e 2 prom) organized as (2048 ? 128 ) bytes ? 64 pages ? 1024 blocks. the device has a 2176 - byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176 - byte increments. the erase operation is impleme nted in a single blo ck unit (128 kbytes ? 8 kbytes: 2176 bytes ? 64 pages). the tc58nvg0s3h ta00 is a serial - type memory device which utilizes the i/o pins for both address and data input/output as well as for command inputs. the erase and program operations are automatically executed making the device most suitable for applications such as solid - state file storage, voice recording, image file memory for still cameras and other systems which require high - density non - volatile memory data storage. features ? organization x8 memor y cell array 2176 ? 64k ? 8 register 2176 ? 8 page size 2176 bytes block size (128 k ? 8k ) bytes ? modes read , reset , auto page program, auto block erase, status read , page copy ? mode control serial input / output command control ? number of valid blocks min 10 04 blocks max 1024 blocks ? power supply v cc ? 2. 7 v to 3.6 v ? acce ss time cell array to register 25 ? s max serial read cycle 25 ns min (cl= 50pf ) ? progra m/erase time auto page program 3 00 ? s /page typ. auto block erase 2.5 ms/block typ. ? operating current r ead (25 ns cycle) 3 0 ma max . program (avg.) 3 0 ma max erase (avg.) 3 0 ma max standby 5 0 ? a max ? package tsop i 48 -p- 1220 - 0.50 (weight: 0.53 g typ.) ? 8 bit ecc for each 512byte is required.
TC58NVG0S3HTA00 2012-08- 31 c 2 pin assignment (top view) pin names i/o1 to i/o8 i/o port chip enable write enable read enable cle command latch enable ale address latch enable write protect ready/busy v cc po wer supply v ss ground nc no connection nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 3 8 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc nc nc nc nc v cc v ss nc nc cle ale nc nc nc nc nc ? 8 ? 8 tc58 n v g0s3hta0 0 by / ry ce re re we wp by / ry we ce wp
TC58NVG0S3HTA00 2012-08- 31 c 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 to v cc ? 0. 3 ( ? 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 1 5 0 c t opr operating temperature 0 to 70 c capacitance * (ta ? 25 c, f ? 1 mhz ) symb0l parameter condition min max unit c in input v in ? 0 v ? 10 pf c out output v out ? 0 v ? ? 10 pf * this parameter is periodically sampled and is not tested for every device. i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control v cc i/o1 v ss i/o8 cle ale row address buffer decoder to address register wp by / ry we ce re
TC58NVG0S3HTA00 2012-08- 31 c 4 valid blocks symbol parameter min typ. max unit n vb number of valid blocks 10 0 4 ? 1024 blocks note: the device occasionally c ontains unusable blocks. refer to application note (13) toward the end of this document. t he first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over lifeti me recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 ? 3.6 v v ih high level input voltage vcc x 0.8 ? v cc ? 0. 3 v v il low level input voltage ? 0. 3 * ? vcc x 0.2 v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta ? 0 to 70 , v cc ? 2.7 to 3.6v ) symbol parameter condition min typ. max unit i il input leakage current v in ? 0 v to v cc ? ? ? 10 ? a i lo output leakage current v out ? 0 v to v cc ? ? ? ? 10 ? a i cco1 serial read current ? v il , i out ? 0 ma, t cycle ? 2 5 ns ? ? 30 ma i cco2 programming current ? ? ? ? 30 ma i cco3 erasing current ? ? ? 30 ma i ccs standby current ? v cc ? 0.2 v , ? 0 v/v cc ? ? 50 ? a v oh high level output voltage i oh ? ? 0. 1 ma vcc C 0.2 ? ? v v ol low level output voltage i ol ? 0.1 ma ? ? 0.2 v i ol ( ) output current of pin v ol ? 0.2 v ? 4 ? ma ce by / ry wp
TC58NVG0S3HTA00 2012-08- 31 c 5 ac characteristics and recommended operating conditions (ta ? 0 to 70 , v cc ? 2.7 to 3.6v ) symbol parameter min max unit t cls cle setup time 12 ? ns t clh cle hold time 5 ? ns t cs setup time 20 ? ns t ch hold time 5 ? ns t wp write pulse width 12 ? ns t als ale se tup time 12 ? ns t alh ale hold time 5 ? ns t ds data setup time 12 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh high hold time 10 ? ns t ww high to low 100 ? ns t rr ready to falling edge 20 ? ns t rw ready to falling edge 20 ? ? ns t rp read pulse width 12 ? ? ns t rc read cycle time 25 ? ns t rea access time ? 20 ns t cea access time ? 25 ns t clr cle low to low 10 ? ns t ar ale low to low 10 ? ns t rho h h igh to output hold time 25 ? ns t rloh low to output hold time 5 ? ns t rhz high to output high impedance ? ? 60 ns t chz high to output high impedance ? 2 0 ns t csd high to ale or cle don t care 0 ? ns t reh high hold time 10 ? ns t ir output - high - impedance - to - fa lling edge 0 ? ns t rhw high to low 30 ? ns t whc high to low 30 ? ns t whr high to low 60 ? ns t r memory cell array to starting address ? 25 ? s t dcbsyr1 data cache busy in read cache (following 31h and 3fh) ? 25 ? s t dcbsyr2 data cache busy in page copy (following 3ah) ? 30 ? s t wb high to busy ? 1 00 ns t rst device reset time (ready /read/program/erase) ? 5 / 5 /10/500 ? s *1: tcls and tals can not be shorter than twp *2: tcs should be longer than twp + 8ns. ce wp we re
TC58NVG0S3HTA00 2012-08- 31 c 6 ac test conditions parameter condition v cc : 2. 7 to 3.6v input level v cc ? 0.2 v , 0.2 v input pulse rise and fall time 3 ns in put comparison level vcc / 2 output data comparison level vcc / 2 output load c l ( 5 0 pf ) ? 1 ttl note: busy to ready time depends on the pull - up resistor tied to the pin. (refer to application note (9) toward the end of this do cument.) programming and erasing characteristics (ta ? 0 to 70 , v cc ? 2.7 to 3.6v ) symbol parameter min typ. max unit notes t prog average programming time ? 300 700 ? s t dcbsyw2 data cache busy time in write cache ( following 15h) ? ? ? ? 700 ? ? s (2) n num ber of partial program cycles in the same page ? ? 4 (1) t berase block erasing time ? 2.5 5 ms (1) refer to application note (12) toward the end of this document. (2) t dcbsyw2 depends on the timing between internal programming time and data in tim e. data output when treh is long, output buffers are disabled by /re=high, and the hold time of data output depend on trhoh (2 5 ns min). on this condition, waveforms look like normal serial read mode. when treh is short, output buffers are not disable d by /re=high, and the hold time of data output depend on trloh ( 5ns min). on this condition, output buffers are disabled by the rising edge of cle,ale,/ce or falling edge of /we, and waveforms look like extended data output mode. by / ry
TC58NVG0S3HTA00 2012-08- 31 c 7 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale hold time t dh setup time t ds i/o : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il cle ale i/o ce we re
TC58NVG0S3HTA00 2012-08- 31 c 8 address input cycle timing diagram data input cycle timing diagra m t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle i/o d in 2175 t dh t ds t dh t ds t cs t cls t ch t cs t alh pa8 to 15 ca8 to 11 : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to 7 t dh t ds t cs t cs ale i/o t dh t ds t wp t wh t dh t ds t wp t wh t wc pa0 to 7 t clh t ch t ch we ce
TC58NVG0S3HTA00 2012-08- 31 c 9 serial read cycle timing diagram status read cycle timing diagram t reh t chz t rhz t rea t rc t rr t rhz t rea t rhz t re a i/o t rhoh t rhoh t rhoh t rp t rp t rp : v ih or v il t cea colu mn addr ess a t cea colu mn addr ess a : v ih or v il * : 70h represents the hexadecimal number t whr t dh t ds t cls t clr t cs t clh t ch t wp status output 70h * t w hc t ir t rea t rhz t chz cle i/o t rhoh t cea ce by / ry re we
TC58NVG0S3HTA00 2012-08- 31 c 10 read cycle timing diagram read cycle timing diagram: when interrupted by t clr 30h pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh cle ale t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n data o ut from col. add. n 00h d out n d out n ? 1 t cea 30h pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh cle ale t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n 00h d out n d out n ? 1 t chz t rhz t rhoh col. add. n t csd t cea by / ry ce ce we re
TC58NVG0S3HTA00 2012-08- 31 c 11 read cycle with data cache timing diagram (1/2) 30h pa8 to 15 pa0 to 7 ca8 to 11 ca0 to 7 i/o t dh t ds t wc t als t alh cle ale t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t als t rc t r r t rea column address n * 00h d out 0 d out 1 tcea page address m d out 31h t dh t ds t wb t dcbsyr1 31h t dh t ds t wb d out 0 t rr t rea t dcbsyr1 t clr t clr tcea page address m col. add. 0 col. add. 0 page address m ? 1 t rw t cs t cls t clh t ch 1 continues to of next page 1 * the column address will be reset to 0 by the 31h command input. t cs t cls t clh t ch t cs t cls t clh t ch t cs t cls t clh t ch we re ce by / ry
TC58NVG0S3HTA00 2012-08- 31 c 12 read cycle with data cache timing diagram (2/2) continues from of last page 1 i/o cle ale d out t clr t wb 31h t dh t ds t wb 31h t dh t ds t rc t rr t rea page address m ? 1 page address m ? x t clr t wb t rc t rr t rea tcea 3fh t dh t ds d out 0 d out 1 d out t rc t rr t rea tcea page address m ? 2 t dcbsyr1 t dcbsyr1 t dcbsyr1 t clr col. add. 0 col. add. 0 col. add. 0 tcea d out 0 d out 1 d out d out 0 d out 1 d out 1 t cs t cls t clh t ch t cs t cls t clh t ch t cs t cls t c lh t ch make sure to terminate the operation with 3fh command. we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 13 column address change in read cycle timing diagram (1/2) t clr i/o t cs t cls t clh t ch t wc t als t alh t r cle ale t dh t ds t dh t ds t alh t wb t cs t cls t clh t ch t als t rc t rea tce a t rr page address p page address p column address a 00h ca0 to 7 t dh t ds ca8 to 11 t dh t ds pa0 to 7 t dh t ds pa8 to 15 t dh t ds 30h d out a d out a ? 1 d out a ? n 1 continues from of next page 1 ce we re by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 14 column address chan ge in read cycle timing diagram (2/2) i/o t cs t cls t clh t ch 05h ca0 to 7 ca8 to 11 t wc t als t alh cle ale t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als t rea d out a ? n t rhw page address p column address b t rc t clr tcea t ir d out b ? n d out b ? 1 d out b 1 continues from of last page 1 t whr ce we re by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 15 data output timing diagram command i/o t rc t dh t rp t rp cle ale t rloh t reh t rea t rhz t rea t cs t cls t clh t ch t rp t rr t rea t rloh t ds t chz t rhoh t rhoh t cea dout dout t alh dout we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 16 auto - program operation timing diagram ca0 to 7 t cls t cls t als t ds t dh cle ale : v ih or v il t clh t ch t cs t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t p rog t wb t ds t alh t als * ) m: up to 2175 (byte input data for ? 8 device). column address n ca8 to 11 d in n d in m * 10h 70h status output pa0 to 7 pa8 to 15 80h d in n+1 we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 17 auto - program operation with data cache timing diagram (1/3) t cls t als t ds t dh 80h cle ale : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t dcbsyw2 d in n d in n+1 t wb 80h t ds 15h t alh t als d in 217 5 1 continues to 1 of next page ca0 to ca11 is 0 in this diagram. ca0 to 7 ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 18 auto - program operation with data cache timing diagram (2/3) : v ih or v il : do not input data while data is being output. t cls t als t ds t dh ca0 to 7 80h cl e ale t clh t ch t cs t cls t ds t dh t alh i/o pa0 to 7 ca8 to 11 t cs 1 continued from 1 of last page t dh t ds t dh t dcbsyw2 d in n d in n+1 t wb 80h t ds 15h t alh t als d in 2175 2 pa8 to 15 ca0 to 7 repeat a max of 62 times (in order to program pages 1 to 62 of a block). we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 19 auto - program operati on with data cache timing diagram (3/3) (note) make sure to terminate the operation with 80h - 10h - command sequence. if the operation is terminated by 80h - 15h command sequence, monitor i/o 6 (ready / busy) by is suing status read command (70h) and make sure the previous page program operation is completed. if the page program operation is completed issue ffh reset before next operation. 70h t cls t als t ds t dh cle ale : v ih or v il t clh t ch t cs t cls t ds t dh t alh i/o : do not input data while data is being output. t cs 2 t dh t ds t dh t prog ( * 1) t wb t ds t alh t als d in 2175 continued from 2 of last page ( * 1) t prog : since the last page programming by 10 h command is initiated after the previous cache program, the t prog during cache programming is given by the following equation. t prog ? t prog of the last page ? t prog of the previous page ? a a ? (command input cycle ? address input cycle ? data input cyc le time of the last page) if a exceeds the t prog of previous page, t prog of the last page is t prog max. 80h ca0 to 7 ca8 to 11 pa0 to 7 pa8 to 15 d in n d in n+1 10h status we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 20 auto block erase timing diagram t cs 60h pa8 to 15 cle ale : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy status read comma nd erase start command status output t alh we re ce by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 21 id read operation timing diagram : v ih or v il cle t c ea ale i/o t a r id read command address 00 maker code device code ` t rea t cls t cs t d s t ch t al h t als t cls t cs t ch t alh t dh 90h 00h 98h t rea f1h t rea t rea see table 5 see table 5 t rea i f fail see table 5 we ce re
tc58n vg0 s3ht a00 2012-08- 31 c 22 pin functions the device is a serial access memory which utilizes time - sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the comman d is latched into the command register from the i/o port on the rising edge of the signal while cle is high. address latch enable: ale the ale signal is used to control loading address information into the internal address registe r. address information is latched into the address register from the i/o port on the rising edge of while ale is high. chip enable: the device goes into a low - power standby mode when goes high during the device is in ready state. the signal is ignored when device is in busy state ( ? l), such as during a program or erase or read operation, and will not enter standby mode even if the input goes high . write enable: the signal is used to control the acquisition of data from the i/o port. read enable: the signal controls serial data output. data is available t rea after the falling edge of . the internal column address counter is also incremented (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/output da ta to and from the device. write protect: the signal is used to protect the device from accidental programming or erasing. the internal voltage regulator is reset when is low. this signal is usually use d for protecting the data during the power - on/off sequence when input signals are invalid. ready/busy: the output signal is used to indicate the operating condition of the device. the signal is in busy state ( = l) during the program, erase and read operations and will return to ready state ( = h) after completion of the operation. the output buffer for this signal is an open drain and has to be pulle d - up to vccq with an appropriate resister. if signal is not pulled - up to vccq( open state ), device operation can not guarantee. wp we by / ry we wp by / ry ce ce re re
tc58n vg0 s3ht a00 2012-08- 31 c 23 schematic cell layout and address assignment the program operation works on page units while the erase operation works on block units . a page consists of 2176 bytes in which 2048 bytes are used for main memory storage and 128 bytes are for redundancy or for other uses. 1 page ? 2176 bytes 1 block ? 2176 bytes ? 64 pages ? (128 k ? 8k ) bytes capacity ? 2176 bytes ? 64 pages ? 1024 blocks an address is rea d in via the i/o port over four consecutive clock cycles, as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 ca0 to ca11: column address pa0 to pa1 5 : page address pa6 to pa1 5 : block address pa0 to pa5 : nand address in block first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l l l ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa 4 pa3 pa2 pa1 pa0 fourth cycle pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 2 176 65536 pages 1024 blocks 2048 2048 128 128 page buffer data cache i/o8 i/o1 64 pages ? 1 block 8i/o
tc58n vg0 s3ht a00 2012-08- 31 c 24 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, command input and data input/output are controlled by the cle, ale, , , and signals, as shown in table 2. table 2. logic table cle ale * 1 command input h l l h * data input l l l h h address input l h l h * serial data output l l l h * during program (busy) * * * * * h during erase (busy) * * * * * h during read (busy ) * * h * * * * * l h ( * 2) h ( * 2) * program, erase inhibit * * * * * l standby * * h * * 0 v/v cc h: v ih , l: v il , * : v ih or v il * 1: refer to application note ( 10 ) toward the end of this document regarding the signal when program or erase inhibit * 2: if is low during read busy, and must be held high to avoid unintended command/address input to the device or read to device . reset or status read command can be i nput during read busy. ce ce re re ce we we we wp wp re
tc58n vg0 s3ht a00 2012-08- 31 c 25 table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 ? ? read 00 30 c o lumn address change in serial data output 05 e0 read with data cache 31 ? read start for last page in read cy cle with data cache 3f ? auto page program 80 10 column address change in serial data input 85 ? auto program with data cache 80 15 read for page copy (2) with data out 00 3a auto program with data cache during page copy (2) 8c 15 auto program for last page during page copy (2) 8c 10 auto block erase 60 d0 id read 90 ? ? status read 70 ? ? ? reset ff ? ? ? table 4. read mode operation states cle ale i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il hex data bit assignment (example) 1 0 0 0 0 0 0 0 8 7 6 5 4 3 2 i/o1 serial data input: 80h ce re we
tc58n vg0 s3ht a00 2012-08- 31 c 26 device operation read mode read mode is set when the "00h" and 30h commands are issued to the command register. between the two comma nds, a start address for the read mode needs to be issued. after initial power on sequence, 00h command is latched into the internal command register. therefore read operation after power on sequence is ex e cuted by the setting of only f our address cyc les and 30h command. refer to the figures below for the sequence and the block diagram (refer to the detailed timing chart.) . random column address change in read cycle a data transfer operation from the cell array to the data cache via page buffer starts on the rising edge of in the 30h command i nput cycle (after the address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the clock from the start address designated in the address input cycle. cell array select page n m m data cache page buffer i/o1 to 8: m ? 2175 select page n m m during the serial data output from the data cache, the column address can be changed by inputtin g a new column address using the 05h and e0h commands. the data is read out in serial starting at the new column address. random column address change operation can be done multiple times within the same page. cle 00h ale i/o busy 30h page address n column address m m m+1 m+2 page address n t r start - address input start - address input cle 00h ale i/o col. m page n busy page n 30h 05h e0h col. m m m ? 1 m m ? 1 m ? 2 m ? 3 m ? 4 page n col. m start from col. m start from col. m t r m ? 2 m ? 3 2 busy we by / ry re ce
tc58n vg0 s3ht a00 2012-08- 31 c 27 read operation with read cache the device has a read operation with data cache that enables the high speed read operation shown below. when the block address changes, this sequence has to be started from the beginning. p age n ? 2 if the 31h command is issued to the device, the data content of the next page is transf erred to the page buffer during serial data out from the data cache, and therefore the tr (data transfer from memory cell to data register) will be reduced. 1 normal read. data is transferred from page n to data cache through page buffer. during this time pe riod, the device outputs busy state for tr max. 2 after the ready/busy returns to ready, 31h command is is sued and data is transferred to data cache from page buffer again. this data transfer takes tdcbsyr1 max and the completion of this time period can be d etected by ready/busy signal. 3 data of page n ? 1 is transferred to page buffer from cell while the data of page n in data cache can be read out by /re clock simultaneously. 4 the 31h command makes data of page n ? 1 transfer to data cache from page buffer af ter the completion of the transfer from cell to page buffer. the device outputs busy state for tdcbsyr1 max.. this busy period depends on the combination of the internal data transfer time from cell to page buffer and the serial data o ut time. 5 data of page n ? 2 is transferred to page buffer from cell while the data of page n + 1 in data cache can be read out by /re clock simultaneously 6 the 3fh command makes the data of page n ? 2 transfer to the data cache from the page buffer after the completion of the tran sfer from cell to page buffer. the device outputs busy state for tdcbsyr1 max.. this busy period depends on the combination of the internal data transfer time from cell to page buffer and th e serial data out time. 7 data of page n ? 2 in data cache can be re ad out, but since the 3fh command does not transfer the data from the memory cell to page buffer, the device can accept new c ommand input immediately after the completion of serial data out. data cache page buffer cell array 1 2 3 3 4 5 5 1 6 7 p age n p age n page n ? 1 p age n 30 h 31 h & clock p age n ? 1 p age n ? 2 p age n ? 1 31 h & clock page n ? 2 3 fh & clock cle 00h ale i/o t r 30h col. m page n 0 1 2 3 31h 31h 0 1 2 3 page address n column 0 2175 page address n ? 1 2175 0 1 2 3 page address n ? 2 2175 3fh 1 2 4 3 5 6 7 t dcbsyr1 t dcbsyr1 t dcbsyr1 column buffer 2 busy re we by / ry ce
tc58n vg0 s3ht a00 2012-08- 31 c 28 auto page program operation the device carries o ut an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, address and data input is shown below. (refer to the detailed timing chart.) random column address change in auto page program operation the column address can be changed by the 85h command during the data input sequence of the auto page program operation. two address input cycles after the 85h command a re recognized as a new column address for the data input. after the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. the random column address change operation can be repea ted multiple times within the same page. the data is transferred (programmed) from the register to the selected page on the rising edge of followi ng input of the 10h command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page program data input read& verification cle 80h ale i/o page p col. m din 10h 70h din din din data status out selected page reading & verification program data input col. m col. m 80h page n col. m 85h din din 10h status din din din din col. m din din 70h 90h busy by / ry ce we re
tc58n vg0 s3ht a00 2012-08- 31 c 29 auto page program operation with data cache the device has an auto page program with data cache operation enabling the high speed program operation shown below. when the block address changes this sequenced has to be started from the beginning. data cache page buffer cell array p age n ? p 1 2 3 4 5 5 6 p age n p age n ? 1 data for p age n ? p 3 data for p age n data for p age n data for p age n ? 1 data for p age n ? 1 p age n ? p ? 1 issuing the 15h command to the device after serial data input initiates t he program operation with data cache 1 data for page n is input to data cache. 2 data is transferred to the page buffer by the 15h command. during the transfer the ready/busy outputs busy state (t dcbsyw2 ). 3 data is programmed to the selected page while the data for page n ? 1 is input to the data cache. 4 by the 15h command, the data in the data cache is transferred to the page buffer after the programming of page n is completed. the device output busy state from the 15h command until the data cache becomes empty. the duratio n of this period depends on timing between the internal programming of page n and serial data input for page n ? 1 (t dcbsyw2 ). 5 data for page n ? p is input to the data cache while the data of the page n ? p ? 1 is being programmed. 6 the programming with da ta cache is terminated by the 10h command. when the device becomes ready, it shows that the internal programming of the page ??? p is completed. note: since the last page programming by the 10h command is initiated after the previous cache program, the tpr og during cache programming is given by the following; t prog ? t prog for the last page ? t prog of the previous page ? ( command input cycle ? address input cycle ? data input cycle time of the previous page) cle ale i/o page n 80h add add status output din 15h 70h din din page n ? 1 80h add add add 1 status output din 15h 70h din din page n ? p 80h add add add 3 4 status output din 10h 70h din din 5 6 add add add t dcbsyw2 t dcbsyw2 t prog (note) 2 by / ry we ce re
tc58n vg0 s3ht a00 2012-08- 31 c 30 pass/fail status for each page programmed by the auto page programming with data cache operation can be detected by the status read operation. ? i/o1 : pass/fail of the current page pro gram operation . ? i/o2 : pass/fail of the previous page program operation . the pass/fail status on i/o1 and i/o2 are valid under the following condition s. ? status on i/o1: page buffer read y /busy is ready state. the page buffer ready/busy is output on i/o6 by status r ead operation or pin after the 10h command ? status on i/o2: data cache read/busy is ready state. the data cache ready/busy is output on i/o7 by status read operation or pin after the 15h command. 80 h 15h 70 h status out page 1 data cache busy page buffer busy page 1 page 2 70 h 70 h page 2 70 h 80 h 15h page n ? 1 80 h 10h page n page n ? 1 page n 70 h 80 h 15h i/o2 => i/o1 => invalid invalid page 1 invalid page n ? 2 invalid inv alid invalid page n ? 1 page n page 1 page 2 70 h if the p age b uffer busy returns to ready before the next 80h command input, and if status read is done during this ready p eriod, the status read provides pass/fail for page 2 on i/o1 and pass/fail result for page1 on i/o2 status out status out status out status out status out example) pin by / ry by ry/
tc58n vg0 s3ht a00 2012-08- 31 c 31 page copy (2) by using page copy (2), data in a page can be copied to another page after the data has been read out. when the block address changes (increments) this sequenced has to be started from the beginning. p age copy (2) operation is as following. 1 data for page n is transferred to the data cache. 2 data for page n is read out. 3 copy page address m is input and if the data needs to be changed , changed data is input. 4 data cache for page m is transferred to the page buffer. 5 after the ready state, data for page n ? p1 is output from the data cache while the data of page m is being programmed. when changing data, changed data is input. 1 3 4 5 2 t r t dcbsyw2 t dcbsyr2 00 c ommand input address ca0 to ca11, pa0 to pa15 (page n) address input 30 address input 8c a data input 15 00 address input 3a data output address ca0 to ca11, pa0 to pa15 (page m) address ca0 to ca11, pa0 to pa15 (page n+p1) a data output col = 0 start col = 0 start data cache page buf fer cell array 1 2 3 4 5 p age n data for p age n data for p age n p age m p age n + p1 data for p age n + p1 data for p age m by ry/
tc58n vg0 s3ht a00 2012-08- 31 c 32 6 copy page address (m ? r1) is input and if the data needs to be changed , changed data is input. 7 after programmi ng of page m is completed, data cache for page m ? r1 is transferred to the page buffer. 8 by the 15h command, the data in the page buffer is programmed to page m ? r1 . data for page n ? p2 is transferred to the data cache. 9 the data in the page buffer is pro grammed to page m ? rn ? 1 . data for page n ? pn is transferred to the data cache. data cache page buffer cell array 6 7 8 p age m data for p age m ? r1 data for p age m ? r1 data for p age n ? p2 data for p age n ? pn p age m ? r1 page n + p2 p age n ? p1 p age m ? rn ? 1 page n ? pn p age m + rn ? 1 9 8 9 6 7 t dcbsyw2 t dcbsyr2 t dcbsyr2 when changing data, changed data is input. c ommand input address ca0 to ca11, pa0 to pa15 (page m+r1) b 00 address input 3a data output address input 8c data input 15 00 address input 3a dat a output address ca0 to ca11, pa0 to pa15 (page n+p2) address ca0 to ca11, pa0 to pa15 (page n+pn) a b a col = 0 start col = 0 start by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 33 10 copy page address (m ? rn) is input and if the data needs to be changed , changed data is input. 11 by issuing the 10h command, the data in the page buffer is programmed to page m ? rn . (*1) since the last page programming by the 10h command is initiated after the previous cache program, the t prog here will be expected as the following, t prog ? t prog of the last page ? tprog of the previous page ? ( command input cycle ? address input cycle + data output/input cycle time of the last page) note) data input is required only if previous data output needs to be altered. if the data has to be changed, locate the desired address with the column and p age address input after the 8ch command, and change only the data that needs be changed. if the data does not have to be changed, data input cycles are not required. make sure is held to high level when page copy (2) operation is pe rformed. also make sure the page copy operation is terminated with 8ch - 10h command sequence data cache page buffer cell array p age m ? rn ? 1 data for p age m ? rn data for p age m ? rn p age m + rn 10 11 10 11 t prog ( *1 ) c omman d input address ca0 to ca11, pa0 to pa15 (page m+rn) address input 8c data input 10 70 status output b b wp by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 34 auto block erase the auto block erase operation starts on the rising edge of after the era se start command d0h which follows the erase setup command 60h . this two - cycle process for erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. the device automatically executes the erase and veri fy operations. pass i/o fail 60 d0 70 block address input: 2 cycles status read command busy erase start command we by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 35 id read the device contains id codes which can be used to identify the device type, the manufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 1 1 0 0 0 1 f 1 h 3rd data chip number, cell type 1 0 0 0 0 0 0 0 80h 4th data page size, block size, 0 0 0 1 0 1 0 1 15h 5th data plane number 0 1 1 1 0 0 1 0 72h 3rd data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 reserved 1 0 0 0 00h 98h f1h see table 5 see table 5 cle t cea ale i/o t ar t rea id read command address 00 maker code devi ce code see table 5 90h 3rd data 4th data 5th data we ce re
tc58n vg0 s3ht a00 2012-08- 31 c 36 4th data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 1 kb 2 kb 4 kb 8 kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64 kb 128 kb 256 kb 512 k b 0 0 1 1 0 1 0 1 i/o width x8 x16 0 1 reserved 0 0 1 5th data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 plane number 1 plane 2 plane 4 plane 8 plane 0 0 1 1 0 1 0 1 reserved 0 1 1 1 1 0
tc58n vg0 s3ht a00 2012-08- 31 c 37 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port using after a 70h command input. the status read can also be used during a re ad operation to find out the ready/busy status. the resulting information is outlined in table 6. table 6. status output table definition page program block erase cache program read cache read i/o1 chip status1 pass: 0 fail: 1 pass/fail pass/fail invali d i/o2 chip status 2 pass: 0 fail: 1 invalid pass/fail invalid i/o3 not used 0 0 0 i/o4 not used 0 0 0 i/o5 not used 0 0 0 i/o6 page buffer ready/busy ready: 1 busy: 0 ready/busy ready/busy ready/busy i/o7 data cache ready/busy ready: 1 busy: 0 ready /busy ready/busy ready/busy i/o8 write protect not protected :1 protected: 0 write protect write protect write protect the pass/fail status on i/o1 and i/o2 is only valid during a program/erase operation when the device is in the ready state. chip statu s 1: during a auto page program or auto block erase operation this bit indicates the pass/fail result. during a auto page programming with data cache operation, this bit shows the pass/fail results of the current page program operation , and therefore this bit is only valid when i/o6 shows the ready state. chip status 2: this bit shows the pass/fail result of the previous page program operation during auto page programming with data cache. this status is valid when i/o7 shows the ready state. the status out put on the i/o6 is the same as that of i/o7 if the command input just before the 70h is not 15h or 31h . re
tc58n vg0 s3ht a00 2012-08- 31 c 38 an application example with multiple devices is shown in the figure below. system design note: if the pin signals from mult iple devices are wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. reset the reset mode stops all operations. for example, in case of a program or erase operation, the internal ly generated voltage is discharged to 0 volt and the device enters the wait state. reset during a cache program/page copy may not just stop the most recent page program but it may also stop the previous program to a page depending on when the ff reset is i nput. the response to a ffh reset command input during the various device operations is as follows: when a reset (ffh) command is input during programming internal v pp 80 10 ff 00 t rst (max 10 ? s) device 1 cle device 2 device 3 device n device n ? 1 ale status on device 1 70h ale i/o 70h status on device n cle busy i/o1 to i/o8 3 ce by / ry 1 ce 1n ce ? re n ce by / ry we 2 ce
tc58n vg0 s3ht a00 2012-08- 31 c 39 when a reset (ffh) command is input during erasing when a reset (ffh) command is input duri ng read operation when a reset (ffh) command is input during ready when a status read command (70h) is input after a reset when two or more reset commands are input in succession 10 ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff i/o status : pass/fail ? pass : ready/busy ? ready ff 70 00 ff 00 t rst (max 5 ? s) 30 internal erase voltage d0 ff 00 t rst (max 500 ? s) 00 t rst (max 5 ? s) ff by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 40 application notes and comments (1) power - on/off sequence: the timing sequence shown in the figure below is necessary for the power - on/off sequence. the device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. during the initialization the device ready/busy signal in dicates the busy state as shown in the figure below. in this time period, the acceptable commands are ffh or 70h. the signal is useful for protecting against data corruption at power - on/off. (2) power - on reset th e following sequence is necessary because some input signals may not be stable at power - on. (3) prohibition of unspecified commands the operation commands are listed in table 3. input of a command other than those specified in table 3 is prohibited. stored d ata may be corrupted if an unknown command is entered during the command cycle. (4) restriction of commands while in the busy state during the busy state, do not i nput any command except 70h and ffh. ff reset power on v il operation 0 v v cc 2.7 v 2.5 v v il don t care don t care v ih , , cle, ale invalid ready/bus y 1 ms max 100 ? s max don t care invalid 1 ms max 100 ? s max 1ms 2.7 v 2.5 v 0.5 v 0.5 v invalid wp wp we ce re
tc58n vg0 s3ht a00 2012-08- 31 c 41 (5) acceptable commands after serial input command 80h once the serial input command 80h has been input, do not input any command other than the column address change in serial data input command 85h , auto program command 10h , auto program with data cache command 15h , or the reset command ffh . if a command other than 85h , 10h , 15h or ffh is input, the program operation is not performed and the device operation is set to the mode which the input command specifies. (6) addressing for program operation within a block, the pages mu st be programmed consecutively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the block. random page address programming is prohibited. command other than 85h , 10h , 15h or ffh 80 programming cannot be executed. 10 xx mode specified by the command. 80 ff address input data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (1) (2) (3) (32) (64) data (64) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (2) (32) (3) (1) (64) data (64) ex.) random page program (prohibition) we by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 42 (7) status read during a read operation the device status can be read ou t by inputting the status read command 70h in read mode. once the device has been set to status read mode by a 70h command, the device will not return to read mode unless the read command 00h is input ted during [a]. if the read command 00h is input ted during [a], status read mode is reset, and the device returns to read mode. in this case, data output starts automatically from address n and address input is unnecessary (8) auto programming failure (9) : termination for the ready/ busy pin ( ) a pull - up resistor needs to be used for termination because the buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to ad dress n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary from device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r c l 1.5 ? s 1.0 ? s 0.5 ? s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc ? 3.3 v ta ? 25 c c l ? 5 0 pf t f ready v cc t r busy 00 address n command [a ] status read command input status read status output . 70 00 30 by / ry by / ry ce re by / ry we
tc58n vg0 s3ht a00 2012-08- 31 c 43 (10) note regarding the signa l the erase and program operations are automatically reset when goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing t ww (100 ns min) 80 10 din t ww (100 ns min) 60 d0 din t ww (100 ns min) 80 10 din t ww (100 ns min) 60 d0 din wp we wp by / ry
tc58n vg0 s3ht a00 2012-08- 31 c 44 (11) when five address cycle s are input although the device may read in a fifth address, it is ignored inside the chip. read operation program operation cle ale i/o address input ignored 80h data input cle address input 00h ale i/o ignored 30h ce by / ry we
tc58n vg0 s3ht a00 2012-08- 31 c 45 (12) several programming cycles on the same page (partial page program) each segment can be programmed individually as follows: data pattern 4 data pattern 1 all 1 s all 1 s all 1 s all 1 s 1st programming 2nd programming 4th programming result data pattern 1 data pattern 2 data pattern 4 data pattern 2
tc58n vg0 s3ht a00 2012-08- 31 c 46 (13) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: please do not perform an erase operation to bad blocks. it may be impossible to recover the bad bl ock information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by th e system. a bad block does not affect the performance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over the device lifetime is as follows: min typ. max unit valid (good) block number 10 0 4 ? ? 1024 bl ock bad block test flow regarding invalid blocks, bad block mark is in whole pages. please read one column of any page in each block. if the data of the column is 00 (hex), define the block as a bad block . * 1: no erase operation is allowed to detected bad blocks bad block bad block pass read check start bad block * 1 last block end yes fail block no ? 1 no block no. ? block no. ? 1
tc58n vg0 s3ht a00 2012-08- 31 c 47 (14) failure phenomena for program and erase operations the d evice may fail during a program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase ? blo ck replacement page programming failure status read after program ? block replacement read bit error ecc correction / block refresh ? ecc: error correction code. 8 bit correction per 5 1 2 bytes is necessary. ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using the device when the battery is low. power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate sche me). block a block b error occurs buffer memory
tc58n vg0 s3ht a00 2012-08- 31 c 48 (16) reliability guidance this reliability guidance is intended to notify some guidance related to usi ng nand flash with 8 bit ecc for each 512 bytes . for detailed reliability data, please refer to toshiba s reliability note. although random bit errors may occur during use, it does not necessarily mean that a block is bad. generally, a block should be marked as bad when a program status failure or erase status failure is detected. the other failure modes may be recovered by a block erase. ecc treatment for read data is mandatory due to the following data retention and read disturb failures. ? write/eras e endurance write/erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto program or auto block erase operation. the cumulative b ad block count will increase along with the number of write /erase cycle s . ? data retention the data in memory may change after a certain amount of storage time. t his is due to charge loss or charge gain. after block erasure and reprogramming, the block may become usable again. here is the combined characteristi cs image of write/erase endurance and data retention. ? read disturb a read operation may disturb the data in memory . the data may change due to charge gain. usually , bit errors occur on other pages in the block, not the page being re ad. after a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. after block erasure and reprogramming, the block may become usable again. write/erase endurance [cycle s ] data retention [year s ]
tc58n vg0 s3ht a00 2012-08- 31 c 49 package dimensions weight: 0.53 g (typ.)
tc58n vg0 s3ht a00 2012-08- 31 c 50 revision history date rev. description 20 12 - 02 - 1 7 0 . 1 0 initial release 2012 - 0 7 - 06 0.20 described ecc bit number: 8, changed tberase, revised id table, corrected typo. 2012 - 08 - 31 1.00 deleted tentative /tbd notation.
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